About the Role

In this role you are responsible for system level and integration verification of the designs, as they are produced by the RTL design team. You will also have to provide feedback during the architecture exploration process for future generation designs.

What you will do:

• verification of low power, multi clock domain designs
• working with ~20 nm class digital technologies
• helping RTL designers with module level functional verification

What you should bring in:

• willingness to learn new, potentially unconventional, technologies/techniques
• experience in verification of multi clock domain designs
• some experience in working with mixed signal systems

Helpful but not required:

• experience with the Chisel hardware design language
• experience using the Cadence suite of tools
• experience in working with designs beyond the standard cell libraries
• experience with modern software development tools (e.g. python, git)
• experience with heterogeneous integration technologies